Giga Hertz range frequency synthesizers using a phase-locked loop (PLL) need high-speed multi-modulus frequency dividers which divide input frequency by a selected one of a plurality of division ratios. In a known high-speed multi-modulus frequency divider, an input division ratio N is applied to a decoder having a look-up table which provides appropriate values M and K, so that values M and K are programmably set to the M and K programmable counters, respectively. A dual-modulus counter (DMC) divides input frequency fin and its output of a divided frequency is provided to the K and M counters. The DMC selects its division ratio P or P+1 in response to the count of the K counter. Value K is any value between 0 to P-1. If value K is greater than zero, the division ratio of the DMC is set to P+1 at the start of the cycle. The divided output of the DMC clocks the two counters. When the count of the K counter reaches its programmed value K, it ceases counting and the division ratio of the DMC is set to P. When the count of the M counter reaches its programmed value M, the M and K counters are reset and the cycle repeats. A divided frequency fout is provided by the M counter. A total division ratio Rdiv of the frequency divider is given by: EQU Rdiv=fin/fout=K(P+1)+(M-K)P
or EQU Rdiv=fin/fout=MP+K (1)
A drawback is that it requires the decoder which needs a great number of input bits, resulting in a complicated circuit. For example, the frequency divider needs a large number of bits to divide numbers as high as 262,143. Specifically, the decoder needs 18 input bits. One solution is to choose P equal to a power of two (P=2.sup.k). The total division ratio Rdiv of the frequency divider is given by: EQU Rdiv=fin/fout=M(2.sup.k)+K (2)
Because the k least significant bits (LSBs) of the input division ratio word can be directly used as the program inputs to the K counter and the remaining bits of the input word can be directly used as the program input to the M counter, no decoder is required. The largest modulus of a counter with n flip-flops is 2.sup.n. In order to count to 2.sup.n+1, an additional flip-flop is necessary for the input stage of the counter, the additional flip-flop being clocked with a high input frequency. Because of high input frequency (e.g., GHz range), it requires high speed circuits of bipolar transistors, resulting in a large amount of power consumption. This is a drawback of the DMC having division ratios of P/P+1, P being a power of two (P=2.sup.k).